A logic state is stored in a cell by programming its threshold voltage. In non-volatile memory devices this is done by transferring a certain electrical charge in a floating gate of the cell.
The storage capacity of memory devices can be multiplied by storing more than one bit of information in each single cell of the same physical structure as if intended to store a single information bit. This is in addition to increasing the integration density of arrays of cells individually addressable through wordlines and bit-lines of the array.
Though based on the same physical mechanisms, the programming and reading of cells that store more than one bit (multi-level cells) are carried out with techniques that differ from those used for cells that store a single bit (two-level cells).
To read a two-level memory array cell, a certain voltage is applied to the control gate (wordline) of the cell. The value of such a reading voltage is between the threshold voltage of an erased cell and the threshold voltage of a programmed cell such that when the cell is programmed, the reading voltage is lower than its threshold voltage. As a consequence, no current flows through the cell. In contrast, when the cell is erased, the reading voltage is higher than its threshold voltage, and thus a current flows through the cell.
In four-level cells, two bits of information may be stored by making the programming voltages of the different thresholds that may be set for one memory cell define four different intervals. Each interval is associated to a respective two-bit datum. A reading operation is carried out by comparing an electrical parameter, correlated with the current that flows through the cell, with four distinct reference intervals. The reference intervals are defined by the three different thresholds that may be programmed for each single cell. Each one is associated to a respective two-bit datum. The logic datum associated to the distinct interval of values (threshold voltage distributions) in which the measured electrical parameter falls is thus determined.
This approach for a multi-level operation of the cells is applicable to volatile memory cells, such as DRAMs, as well as to non-volatile memory devices, such as EEPROMs and FLASH-EPROMs.
Of course, incrementing the number of information bits that may be stored in a single memory cell makes certain functioning characteristics of the memory array cells more critical, such as their immunity to disturbances (noise), to the spread of information retention characteristics, and to ensure appropriate tolerance ranges of the biasing voltages at which each cell is programmed and read.
A basic circuit scheme of two memory array bitlines and a so-called page buffer of a four-level FLASH memory is depicted in FIG. 1 and it is described in great detail in European Patent Application No. 05106972.2. This application is assigned to the current assignee of the present invention, the contents of which are incorporated herein by reference in its entirety. The page buffer manages the operations of reading the information stored in the memory cells of a selected memory page, or of writing new information in the cells.
The page buffer includes a buffer register of the same size (capacity) of that of a memory page, in which data read (in parallel mode) from the memory cells of a selected memory page are temporarily stored, before being serially output. Similarly, when data are to be written in a memory page, the page buffer is replenished with data that are thereafter written in parallel in the memory cells of a selected memory page. Therefore, a page buffer normally includes a relatively large number of volatile storage elements, typically bistable elements or latches, in a number corresponding to the number of memory cells of the memory page.
The basic operations that usually are performed on the memory cells are a page read (an operation involving reading data from a selected memory page), a page program (writing data into a selected memory page), and an erase operation, wherein the content of the memory cells is erased.
In four-level memory devices, a two-bits datum may be stored in each cell by programming the latter in any one of four different states. Each one is associated with a corresponding logic value of the two-bits datum. Usually, the programming state of a memory cell is defined by the threshold voltage value of the transistor structure that is included in the memory cell structure.
In a memory cell adapted to store two bits, the threshold voltage values of the memory cells may assume one of four different values (or ranges of values). A typical choice is to associate the logic values of the stored bit pair to the four different states according to a binary sequence 11, 10, 01, 00 as shown in FIG. 2, corresponding to increasing threshold voltage values, with the logic value 11 being associated to the state of lowest threshold voltage value (erased state), and the others associated in succession to states of increased threshold voltage value.
Naturally, for writing data into a two-bit memory cell or for reading data therefrom, it might be necessary to perform up to three read accesses to the memory cells using different read voltage references.
A known approach for reducing the number of read accesses necessary to retrieve the stored data includes using a different association rule between logic values and states, that make use of the Gray code, as depicted in FIG. 2. In this way, the logic values are associated to the threshold states according to the binary sequence 11, 10, 00, 01 with the logic value 11 being associated to the erased state, and the others associated in succession to states of increased threshold voltage values.
The main feature of using the Gray code is the fact that adjacent programmed states (in terms of threshold voltage values) have corresponding logic values that differ from each other by only one bit.
In the ensuing description reference will be made to embodiments that employ such a coding, but the same considerations that will be made apply to any kind of coding for storing a two-bit datum in a cell of a four-level memory device.
In order to discriminate the value stored in the cell, the read voltages Vread0, Vread1 and Vread2 should be sufficiently distant from the upper and lower bounds of the distributions of the threshold voltages of the cells, as depicted in FIG. 3.
The cells of a memory page are programmed in parallel by incrementing stepwise their threshold voltage. They do not reach at the same time the desired distributions because there are cells that are faster than the others and require fewer program pulses to reach the programmed threshold. After each program pulse, the cells are read for verifying whether they have been correctly programmed or not. When a cell is found to have a threshold voltage comprised in the desired distribution, it is considered programmed and a configuration switch associated to it is opened so that the programmed cell will not receive any further program pulse.
After having programmed and verified the cells, it is often found that some cells inexplicably no longer have a threshold voltage comprised in the distribution to which they were programmed, and therefore the datum stored therein is not the correct one. More precisely, it appears that the threshold voltage of the fastest cells, that is, the cells that reached first the desired distribution have decreased while the remaining cells were given additional program pulses.
For better understanding the problem, let us refer to the circuit of FIG. 4 and consider a sample case in which all the cells of the wordline WL<31> should be programmed to the logic state 10. All the cells are initially in the erased state, that is, in the state 11. The cell MC31 is subjected to program pulses until its threshold voltage surpasses the voltage VVFY1.
This is carried out by applying the voltage VVFY1 on the wordline WL<31> and stopping to apply further program pulses to the cell MC31 when there is not anymore current flowing through the cell. In this situation, the cell MC31 is considered to have been programmed to the binary logic state 10.
Unfortunately, it may happen that the read margins, that is the difference between the lower bound voltage of the distribution corresponding to the state 10 and a pre-established read voltage Vread0 be smaller than the design value.
What happens is schematically illustrated in FIG. 5. The cell is initially erased (a) and must be programmed in the state 10 while ensuring a certain read margin. Program pulses are provided to the cell (b) and a threshold voltage greater than the level VVER1 is eventually verified. When other cells of the same bitline have been programmed, it seems as the threshold voltage of the cell appears to have shifted to the left (c) and the read margin may become smaller than the designed safe value (d).